SFF-8636 lower page 00h register map

The lower 128 bytes of a QSFP+/QSFP28 module are always visible and hold what a host touches at runtime: identifier and revision, interrupt flags, module and per-lane monitors, Tx disable, rate and application select, power control, CDR control, masks, passwords and the page-select byte. This page lists them byte by byte and bit by bit, compiled against SFF-8636 Rev 2.11 (fields introduced in Rev 2.10 are marked rev 2.10). Narrative: SFF-8636; the identity block is in Upper page 00h map.

Legend: rsvd = reserved · vendor = vendor specific · lanes are numbered 1–4; in per-lane bytes bits 7–4 = lanes 4,3,2,1 of the first group and bits 3–0 = lanes 4,3,2,1 of the second group unless stated otherwise · flags are latched, cleared on read.

Identification and status — bytes 0–2

Byte	Field	Bits
0	Identifier	SFF-8024 Table 4-1: 0Ch QSFP · 0Dh QSFP+ · 11h QSFP28 · 1Eh QSFP with CMIS (then the CMIS map applies)
1	Revision compliance	00h unspecified · 01h SFF-8436 ≤ 4.8 · 02h SFF-8436 ≤ 4.8 with 186–189 per SFF-8636 · 03h SFF-8636 ≤ 1.3 · 04h 1.4 · 05h 1.5 · 06h 2.0 · 07h 2.5/2.6/2.7 · 08h 2.8/2.9/2.10 — Specification revisions
2	Status indicators	7–3 rsvd · 2 Flat_mem (1 = only page 00h) · 1 IntL (1 = interrupt asserted, read-only mirror of the pin) · 0 Data_Not_Ready

Interrupt flags — bytes 3–21

Byte	Flag group	Bits
3	LOS	7 L-Tx4 LOS · 6 L-Tx3 LOS · 5 L-Tx2 LOS · 4 L-Tx1 LOS · 3 L-Rx4 LOS · 2 L-Rx3 LOS · 1 L-Rx2 LOS · 0 L-Rx1 LOS
4	Tx fault / adaptive EQ fault	7 L-Tx4 adaptive EQ fault · 6 L-Tx3 · 5 L-Tx2 · 4 L-Tx1 adaptive EQ fault · 3 L-Tx4 fault · 2 L-Tx3 fault · 1 L-Tx2 fault · 0 L-Tx1 fault
5	LOL (CDR lock)	7 L-Tx4 LOL · 6 L-Tx3 · 5 L-Tx2 · 4 L-Tx1 LOL · 3 L-Rx4 LOL · 2 L-Rx3 · 1 L-Rx2 · 0 L-Rx1 LOL
6	Temperature	7 temp high alarm · 6 temp low alarm · 5 temp high warning · 4 temp low warning · 3–1 rsvd · 0 initialisation complete flag rev 2.x
7	Vcc	7 Vcc high alarm · 6 Vcc low alarm · 5 Vcc high warning · 4 Vcc low warning · 3–0 rsvd
8	vendor	—
9	Rx power lanes 1–2	7 Rx1 power high alarm · 6 Rx1 low alarm · 5 Rx1 high warning · 4 Rx1 low warning · 3 Rx2 high alarm · 2 Rx2 low alarm · 1 Rx2 high warning · 0 Rx2 low warning
10	Rx power lanes 3–4	same layout for Rx3 (7–4) and Rx4 (3–0)
11	Tx bias lanes 1–2	same layout: Tx1 bias (7–4), Tx2 bias (3–0)
12	Tx bias lanes 3–4	Tx3 (7–4), Tx4 (3–0)
13	Tx power lanes 1–2	Tx1 power (7–4), Tx2 power (3–0)
14	Tx power lanes 3–4	Tx3 (7–4), Tx4 (3–0)
15–16	rsvd	—
17–21	vendor	vendor-specific flags

Module monitors — bytes 22–33

Bytes	Monitor	Format
22–23	Temperature	signed 16-bit, 1/256 °C
24–25	rsvd	—
26–27	Vcc	unsigned 16-bit, 100 µV
28–29	rsvd	—
30–33	vendor	—

Channel monitors — bytes 34–81

Bytes	Monitor	Format
34–35 / 36–37 / 38–39 / 40–41	Rx1 / Rx2 / Rx3 / Rx4 power	unsigned 16-bit, 0.1 µW
42–43 / 44–45 / 46–47 / 48–49	Tx1 / Tx2 / Tx3 / Tx4 bias	unsigned 16-bit, 2 µA
50–51 / 52–53 / 54–55 / 56–57	Tx1 / Tx2 / Tx3 / Tx4 power	unsigned 16-bit, 0.1 µW
58–65	rsvd	—
66–81	vendor	—
82–85	rsvd	—

Per-lane interpretation: Per-lane diagnostics.

Controls — bytes 86–99

Byte	Field	Bits
86	Tx disable	7–4 rsvd · 3 Tx4 disable · 2 Tx3 · 1 Tx2 · 0 Tx1 disable (1 = laser off)
87	Rx rate select	7–6 Rx4 rate select · 5–4 Rx3 · 3–2 Rx2 · 1–0 Rx1 (2-bit code per lane; 00 = lowest rate group) — Rate select
88	Tx rate select	7–6 Tx4 · 5–4 Tx3 · 3–2 Tx2 · 1–0 Tx1
89	Rx4 application select	application code from page 01h (SFF-8079 model); 00h = none
90	Rx3 application select	—
91	Rx2 application select	—
92	Rx1 application select	—
93	Power control	7–4 rsvd · 3 power class 8 enable rev 2.10 · 2 high power class enable (classes 5–7) · 1 Power_set (1 = low power mode; effective when bit 0 = 1) · 0 Power_override (1 = software controls power mode instead of the LPMode pin)
94	Tx4 application select	—
95	Tx3 application select	—
96	Tx2 application select	—
97	Tx1 application select	—
98	CDR control	7 Tx4 CDR on · 6 Tx3 · 5 Tx2 · 4 Tx1 CDR on · 3 Rx4 CDR on · 2 Rx3 · 1 Rx2 · 0 Rx1 CDR on (1 = CDR enabled, 0 = bypass) — CDR
99	Signal control rev 2.10	7–2 rsvd · 1 LPMode/TxDis input pin function (0 = LPMode, 1 = TxDis) · 0 IntL/LOSL output pin function (0 = IntL, 1 = LOSL); availability advertised in upper byte 193

Masks — bytes 100–106

A mask bit set to 1 prevents the corresponding flag from asserting IntL.

Byte	Masks for	Bit layout
100	LOS flags	as byte 3
101	Tx fault / adaptive EQ fault	as byte 4
102	LOL flags	as byte 5
103	Temperature flags	7–4 as byte 6 bits 7–4 · 0 initialisation-complete mask
104	Vcc flags	as byte 7
105	vendor	—
106	vendor	—

Rx power, Tx bias and Tx power masks are on page 03h bytes 242–247.

Extended controls and passwords — bytes 107–127

Byte	Field	Contents
107	Max power rev 2.10	maximum power consumption in 0.1 W units, valid for power class 8 (upper byte 129 bit 5)
108–109	Propagation delay rev 2.10	cable assemblies: delay in units of 10 ns
110	Advanced low-power mode rev 2.10	bits 3–0 advertise/control an intermediate low-power class (per revision)
111–112	rsvd	—
113–118	rsvd / vendor	—
119–122	Password change entry	vendor-defined (write new password)
123–126	Password entry	vendor-defined; typical unlock area — Write-protection types
127	Page select	00h identity · 01h application select table · 02h user EEPROM · 03h thresholds & channel controls · 20h–21h optional; write before reading 128–255

Reading a QSFP28 lower page in practice

Byte 0 = 11h, byte 1 = 06h or 08h → SFF-8636 rev 2.x QSFP28; byte 2 bit 0 = 0 → data ready.
Bytes 3–14 all 00h → no LOS, fault, LOL or threshold flags (read twice: the first read clears latched history).
Bytes 34–57 → four Rx powers, four bias currents, four Tx powers; compare lanes with each other (Typical values).
Byte 86 = 00h → all lasers enabled; byte 93 bit 1 = 0 → high power; byte 98 = FFh → all CDRs on.
Byte 127 = 00h → upper page shows identity (Upper page 00h map).

SFF-8472 A2h map — the SFP equivalent.
CMIS lower page — the CMIS equivalent.
Memory map quick reference.