What the host does: discovery, validation, bring-up

The specifications describe the module's side — pins, memory, states. This page describes the host's side: the sequence a switch, router or NIC runs from the moment a module is inserted until traffic flows, with the pins, bytes and timings each step uses. Knowing it turns "the port says unsupported" into "the host stopped at step 4", and explains why a module that is perfect on the bench can still fail in a port.

Low-speed signals by form factor

Form factor	Presence	Reset / power	Interrupt / fault	Other
SFP / SFP+ / SFP28	MOD_ABS (low = present)	— (TX_DISABLE gates the laser)	TX_FAULT, RX_LOS	RS0, RS1 rate select
XFP	Mod_ABS	P_Down/RST	Interrupt, Mod_NR (not ready), RX_LOS	TX_DIS, Mod_DeSel
QSFP+ / QSFP28	ModPrsL	ResetL, LPMode	IntL	ModSelL
QSFP-DD	ModPrsL	ResetL, LPMode	IntL	ModSelL
OSFP	PRSn	RSTn, LPWn	INT	— (no select pin, one bus per port)
SFP-DD	module absent as SFP	low-power request	interrupt	rate select as SFP

Pin functions and pinouts per family: SFP hardware, QSFP hardware, XFP.

The sequence

#	Step	SFP (SFF-8472)	QSFP (SFF-8636)	CMIS	Failure looks like
1	Detect	MOD_ABS goes low; debounce	ModPrsL low	ModPrsL / PRSn low	port stays empty; module "not detected"
2	Power & wait	3.3 V is always on; wait t_init 300 ms	power on with LPMode high (class 1 only); wait t_init 2 s or poll Data_Not_Ready	same; wait for module state to leave MgmtInit (≤ 2 s)	reads return FFh / 00h; identity blank
3	Identify	read A0h 0–95; byte 0 = 03h selects the SFF-8472 parser	read 0–127 and upper 00h; byte 0 = 0Dh/11h, byte 1 revision	read lower page and upper 00h; byte 0 = 18h/19h…, byte 1 CMIS version	unknown module type
4	Validate	CC_BASE, CC_EXT; identifier/connector/encoding consistency	CC_BASE, CC_EXT	page 00h checksum	invalid EEPROM, checksum error — Checksums
5	Decode type	compliance bytes 3–10, 36; rate byte 12/66; lengths; wavelength	bytes 131–138, 192; 140/222	media type 85, application descriptors	speed and type not supported — Compliance codes
6	Policy	vendor name/PN (and possibly signature) against the compatibility table	same	same	unsupported transceiver, errdisable — Vendor lock
7	Power class	byte 64 level bits vs port budget	byte 129 class; write byte 93 to release low power / enable classes 5–8	byte 200 class vs port; deassert LPMode or clear LowPwrRequestSW → module PwrUp → Ready	held in low power, power exceeds — Power & thermal
8	Configure	RS0/RS1 or soft rate select; host-side speed, FEC, SGMII/1000BASE-X	CDR on/off (98), rate select (87–88), breakout lanes on the host	pick AppSel/DataPathID in staged control set → ApplyDPInit → data path Init → Initialized	LOL, FEC mismatch, breakout refused — Speed & rate
9	Enable Tx	TX_DISABLE pin low or soft bit clear (A2h 110.6)	byte 86 = 00h	page 10h byte 130 = 00h → DPTxTurnOn → DPActivated	far end sees −40 dBm — No link checklist
10	Link	PHY/MAC sees signal; AN/link training on DAC	same per lane	same per data path	link down with good levels
11	Monitor	poll A2h monitors and flags every few seconds; TX_FAULT / RX_LOS pins	IntL → read flags 3–21; poll monitors	IntL → module flags + page 11h lane flags; VDM	alarms, flaps — DDM levels, Link flapping
12	Remove	MOD_ABS high → tear down	ModPrsL high	ModPrsL high	stale state if debounce misses

Steps 3–6 happen in low power for QSFP and CMIS modules: the host validates before it spends power on optics. That is why a locked or mis-coded module never lights its laser, and why the far end reads −40 dBm on a module that is electrically fine.

Timings the host waits for

Wait	SFP	QSFP	CMIS
Management ready after insertion	300 ms	2 s	≤ 2 s (MgmtInit) then state LowPwr
After releasing low power	—	until Data_Not_Ready clears	until module state Ready (max duration advertised in page 01h)
Data path init	—	—	advertised per step (nibble code: < 1 ms … < 50 min)
Tx enable to light	t_on ≤ 1 ms	ton_txdis 100 ms / toff 400 ms	DPTxTurnOn duration advertised
Flag to interrupt	—	ton_IntL 200 ms	as hardware spec

Bus-level timings (t_WR, clock stretch): Two-wire interface.

Policy points where hosts differ

Whitelist strictness — from "vendor name only" to signed vendor-specific blocks.
What happens on rejection — port disabled, laser off, or link allowed with a log entry (Third-party optics).
CMIS depth — full application/data-path control vs "release LPMode and hope" (CMIS issues).
FEC and speed defaults — derived from compliance codes or configured statically.
DDM polling — interval, whether thresholds trigger port shutdown, whether external calibration is applied (Calibration).

Per-vendor CLI to see where the host stopped: Verifying optics on switches.

How a programmer differs from a host

A programmer such as CodingBox runs steps 1–5 and 11 but no policy: it reads everything the module exposes, including vendor areas and password bytes, keeps CMIS modules in low power unless asked otherwise, and never enables the laser by itself. That is why a module can look healthy on the bench and still fail in a port — the bench has no step 6.

In CodingBox

Check transceiver shows the result of steps 3–5 as a host would see them — type, rate, checksums, power class — and flags inconsistencies before the module reaches a port; DDM covers step 11 with live monitors and flags.